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Cache Coherence Support for Non­Shared Bus Architecture on Heterogeneous MPSoCs - Technical Paper



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Abstract

Paper by Taeweon Suh, Daehyun Kim, and Hsien­Hsin S. Lee.

They propose two novel integration techniques | bypass and bookkeeping in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Theyer RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.

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